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CYUSB3035 ez-usb ? fx3s superspeed usb controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-84160 rev. *b revised june 20, 2013 features universal serial bus (usb) integration ? usb 3.0 and usb 2.0 peripherals compliant with usb 3.0 specification 1.0 ? 5-gbps usb 3.0 phy co mpliant with pipe 3.0 ? high-speed on-the-go (hs-otg) host and peripheral com- pliant with otg supplement version 2.0 ? thirty-two physical endpoints ? support for battery charging spec 1.1 and accessory charger adaptor (aca) detection general programmable interface (gpif? ii) ? programmable 100-mhz gpif ii enables connectivity to a wide range of external devices ? 8- and 16-bit data bus ? as many as 16 configurable control signals mass storage support ? sd 3.0 (sdxc) uhs-1 ? emmc 4.41 ? two ports that can support memory card sizes up to 2tb system i/o expansion with two secure digital i/o (sdio) ports native usb-attach ed storage (uas), mass-storage class (msc), human interface device (hid), full, and turbo-mtp? support fully accessible 32-bit cpu ? arm926ej core with 200-mhz operation ? 512-kb or 256-kb embedded sram additional connectivity to the following peripherals ? i 2 c master controller at 1 mhz ? i2s master (transmitter only) at sampling frequencies of 32 khz, 44.1 khz, and 48 khz ? uart support of up to 4 mbps ? spi master at 33 mhz selectable clock input frequencies ? 19.2, 26, 38.4, and 52 mhz ? 19.2-mhz crystal input support ultra low-power in core power-down mode ? less than 60 a with vbatt on ? 20 a with vbatt off independent power domains for core and i/o ? core operation at 1.2 v ? i2s, uart, and spi oper ation at 1.8 to 3.3 v ? i 2 c operation at 1.2 v 10- 10-mm, 0.8-mm pitch pb-free ball grid array (bga) package ez-usb ? software and development kit (dvk) for easy code development applications digital video camcorders digital still cameras printers scanners video capture cards test and measurement equipment surveillance cameras personal navigation devices medical imag ing devices video ip phones portable media players industrial cameras logic block diagram ?
CYUSB3035 document number: 001-84160 rev. *b page 2 of 50 contents functional overview ..........................................................3 application examples ....................................................3 usb interface ...... .............. .............. .............. .............. ........4 otg ...............................................................................4 renumeration ........................ .......................................5 ez-dtect ........................................................................5 vbus overvoltage protection ...... .............. ........... ........5 carkit uart mode ........................................................5 host processor interface (p-port) ............ .............. ...........6 gpif ii ...........................................................................6 slave fifo interface .....................................................6 asynchronous sram ....................................................6 asynchronous address/data mu ltiplexed ......................7 synchronous admux interface ......................................7 processor mmc (pmmc) slave interface .....................7 cpu ......................................................................................8 storage port (s-port) ..........................................................8 sd/mmc clock stop .....................................................8 sd_clk output clock stop ..........................................8 card insertion and removal detection .........................8 write protection (wp) ....................................................9 sdio interrupt ...............................................................9 sdio read-wait feature ..............................................9 jtag interface ....................................................................9 other interfaces ..................................................................9 uart interface ..............................................................9 i2c interface ..................................................................9 i2s interface ..................................................................9 spi interface ..................................................................9 boot options .....................................................................10 reset ..................................................................................10 hard reset ..................................................................10 soft reset ....................................................................10 clocking ............................................................................11 32-khz watchdog timer clock i nput ............. ..............11 power .................................................................................11 power modes ..............................................................12 configuration options .....................................................15 digital i/os .........................................................................15 gpios .................................................................................15 system-level esd .............................................................15 pin description .................................................................16 absolute maximum ratings ............................................20 operating conditions .......................................................20 ac timing parameters .....................................................22 gpif ii timing .............................................................22 asynchronous sram timing .. ............... .............. .......25 admux timing for asynchronous access ...................28 synchronous admux timing .......................................30 slave fifo interface ...................................................33 synchronous slave fifo write sequence description ...............................................34 asynchronous slave fifo read sequence description ........... ............... .............. .......35 asynchronous slave fifo write sequence description ...............................................36 storage port timing ....................................................38 serial peripherals timing ...... ......................................41 reset sequence ......... .............. ........... ........... ............ .......45 package diagram ..............................................................47 ordering information ........................................................48 ordering code definitions ..... ......................................48 acronyms ..........................................................................49 document conventions ...................................................49 units of measure .........................................................49 document history page .......... .........................................50 sales, solutions, and legal information ........................50 worldwide sales and design supp ort ............ .............50 products ......................................................................50 psoc solutions ...........................................................50
CYUSB3035 document number: 001-84160 rev. *b page 3 of 50 functional overview cypress?s ez-usb fx3s is the next-generation usb 3.0 peripheral controller, providing integrated and flexible features. fx3s has a fully configurable, parallel, general programmable interface called gpif ii, which can connect to any processor, asic, or fpga. gpif ii is an enhanced version of the gpif in fx2lp, cypress?s flagship usb 2.0 product. it provides easy and glueless connectivity to popular interfaces, such as asynchronous sram, asynchronous and synchronous address data multiplexed interfaces, and parallel ata. fx3s has integrated the usb 3.0 and usb 2.0 physical layers (phys) along with a 32-bit arm926ej-s microprocessor for powerful data processing and for building custom applications. it implements an architecture that enables 185-mbps data transfer from gpif ii to the usb interface. fx3s features an in tegrated storage controller and can support up to two independent mass storage devices on its storage ports. it can support sd 3.0 and emmc 4.41 memory cards. it can also support sdio on these ports. an integrated usb 2.0 otg controller enables applications in which fx3s may serve dual roles; for example, ez-usb fx3s may function as an otg host to msc as well as hid-class devices. fx3s contains 512 kb or 256 kb of on-chip sram for code and data. ez-usb fx3s also provides interfaces to connect to serial peripherals such as uart, spi, i 2 c, and i2s. fx3s comes with application development tools. the software development kit comes with application examples for accelerating time to market. fx3s complies with the usb 3.0 v1.0 specification and is also backward compatible with usb 2.0. it also complies with the battery charging specification v1.1 and usb 2.0 otg specification v2.0. application examples in a typical application (see figure 1 ), fx3s functions as a coprocessor and connects to an external processor, which manages system-level functions. figure 2 shows a typical appli- cation diagram when fx3s functions as the main processor. figure 1. ez-usb fx3s as a coprocessor note 1. assuming that gpif ii is configured for a 16-bit data bus (available with certain part numbers; see ordering information on page 48), synchronous interface operating at 100 mhz. this number also includes protocol overheads.
CYUSB3035 document number: 001-84160 rev. *b page 4 of 50 figure 2. ez-usb fx 3s as main processor usb interface fx3s complies with the following specifications and supports the following features: supports usb peripheral functionality compliant with the usb 3.0 specification revision 1.0 and is also backward compatible with the usb 2.0 specification. complies with otg supplement revision 2.0. it supports high-speed, full-speed, and low-speed otg dual-role device capability. as a peripheral, fx3s is capable of superspeed, high-speed, and full-speed. as a host, it is capable of high-speed, full-speed, and low-speed. supports carkit pass-through uart functionality on usb d+/d? lines based on the cea-936a specification. supports up to 16 in and 16 out endpoints. supports the usb 3.0 streams feature. it also supports usb attached scsi (uas) device-c lass to optimize mass-storage access performance. as a usb peripheral, fx3s supports uas, usb video class (uvc), mass storage class (msc), and media transfer protocol (mtp) usb peripheral classes. as a usb peripheral, all other device classes are supported only in the pass-through mode when handled entirely by a host processor external to the device. as an otg host, fx3s supports msc and hid device classes. note when the usb port is not in use, disable the phy and transceiver to save power. figure 3. usb interface signals otg fx3s is compliant with the otg specification revision 2.0. in the otg mode, fx3s supports both a and b device modes and supports control, interrupt, bulk, and isochronous data transfers. fx3s requires an external charge pump (either standalone or integrated into a pmic) to power vbus in the otg a-device mode. the target peripheral list for otg host implementation consists of msc- and hid-class devices. fx3s does not support attach detection protocol (adp). ez-usb fx3s vbatt vbus usb interface ssrx- ssrx+ sstx- sstx+ d- d+ otg_id
CYUSB3035 document number: 001-84160 rev. *b page 5 of 50 otg connectivity in otg mode, fx3s can be configured to be an a, b, or dual-role device. it can connect to the following: aca device targeted usb peripheral srp-capable usb peripheral hnp-capable usb peripheral otg host hnp-capable host otg device renumeration because of fx3s's soft configuration, one chip can take on the identities of multiple distinct usb devices. when first plugged into usb, fx3s enumerates automatically with the cypress vendor id (0x04b4) and downloads firmware and usb descriptors over the usb interface. the downloaded firmware executes an electrical disconnect and connect. fx3s enumerates again, this time as a device defined by the downloaded information. this pat ented two-step process, called renumeration, happens instantly when the device is plugged in. ez-dtect fx3s supports usb charger and accessory detection (ez-dtect). the charger detection mechanism complies with the battery charging specification revision 1.1. in addition to supporting this version of the sp ecification, fx3s also provides hardware support to detect the resistance values on the id pin. fx3s can detect the following resistance ranges: less than 10 less than 1 k 65 k to 72 k 35 k to 39 k 99.96 k to 104.4 k (102 k 2%) 119 k to 132 k higher than 220 k 431.2 k to 448.8 k (440 k 2%) fx3s's charger detects a dedicated wall charger, host/hub charger, and host/hub. vbus overvoltage protection the maximum input voltage on fx3s's vbus pin is 6 v. a charger can supply up to 9 v on vbus. in this case, an external overvoltage protection (ovp) devi ce is required to protect fx3s from damage on vbus. figure 4 shows the system application diagram with an ovp device connected on vbus. refer to ta b l e 7 for the operating range of vbus and vbatt. figure 4. system diagram with ovp device for vbus carkit uart mode the usb interface supports the carkit uart mode (uart over d+/d?) for non-usb serial data transfer. this mode is based on the cea-936a specification. in the carkit uart mode, the output signaling voltage is 3.3 v. when configured for the cark it uart mode, txd of uart (output) is mapped to the d? lin e, and rxd of uart (input) is mapped to the d+ line. in the carkit uart mode, fx3s disables the usb transceiver and d+ and d? pins serve as pass-through pins to connect to the uart of the host processor. the carkit uart signals may be routed to the gpif ii interface or to gpio[48] and gpio[49], as shown in figure 5 on page 6. in this mode, fx3s supports a rate of up to 9600 bps. power subsystem usb connector ez-usb fx3s usb-port 1 8 2 3 4 5 6 7 9 vbus gnd ssrx- ssrx+ sstx- sstx+ d- d+ otg_id vdd vio1 cvddq vio2 vio3 avdd vio5 ovp device vio4 u3txvddq u3rxvddq
CYUSB3035 document number: 001-84160 rev. *b page 6 of 50 figure 5. carkit uart pass-through block diagram host processor interface (p-port) a configurable interface enables fx3s to communicate with various devices such as sensor, fpga, host processor, or a bridge chip. fx3s supports the following p-port interfaces. gpif ii (16-bit) slave fifo interface 16-bit asynchronous sram interface 16-bit asynchronous address/data multiplexed (admux) interface 16-bit synchronous address/data multiplexed (admux) interface processor mmc slave interface compatible with mmc system specification, mmca technical committee, version 4.2 with emmc 4.3 and 4.4 pass-through boot the following sections describ e these p-port interfaces. gpif ii the high-performance gpif ii in terface enables functionality similar to, but more advanced than, fx2lp's gpif and slave fifo interfaces. the gpif ii is a programmable state machine that enables a flexible interface that may functi on either as a master or slave in industry-standard or proprietary interfaces. both parallel and serial interfaces may be implemented with gpif ii. here are a list of gpif ii features: functions as master or slave provides 256 firmware programmable states supports 8-bit and 16-bit parallel data bus enables interface frequencies up to 100 mhz supports 16 configurable control pins when a 16/8 data bus is used. all control pins can be either input/output or bi-directional. gpif ii state transitions are base d on control input signals. the control output signals are driven as a result of the gpif ii state transitions. the int# output signal can be controlled by gpif ii. refer to the gpifii designer tool. the gpif ii state machine?s behavior is defined by a gpif ii descriptor. the gpif ii descriptor is designed such that the required interface specifica- tions are met. 8 kb of memory (separate from the 512 kb of embedded sram) is dedicated to the gpif ii waveform where the gpif ii descriptor is stored in a specific format. cypress?s gpif ii designer tool enables fast development of gpif ii descriptors and includes examples for common inter- faces. example implementations of gpif ii are the asynchronous slave fifo and synchronous slave fifo interfaces. slave fifo interface the slave fifo interface signals are shown in figure 6 . this interface allows an external processor to directly access up to four buffers internal to fx3s. further details of the slave fifo interface are described on page 33. note access to all 32 buffers is also supported over the slave fifo interface. for details, contact cypress applications support. figure 6. slave fifo interface asynchronous sram this interface consists of standard asynchronous sram interface signals as shown in figure 7 on page 7. this interface is used to access both the configuration registers and buffer memory of fx3s. both single -cycle and burst accesses are supported by asynchronous interface signals. the most significant address bi t, a[7], determines whether the configuration registers or buff er memory are accessed. when the configuration registers are selected by asserting the address bit a[7], the address bus bits a[ 6:0] point to a configuration register. when a[7] is deasserted, the buffer memory is carkit uart pass-through carkit uart pass-through interface on gpif ii () rxd (dp) txd (dm) usb phy dp dm txd rxd usb-port mux uart_ txd uart_ rxd gpio[48] (uart_tx) gpio[49] ( uart_rx) ctrl carkit uart pass-through interface on gpios external processor ez-usb fx3s slcs# a[1:0] d[15:0] slrd# sloe# slwr# pktend flaga flagb note: multiple flags may be configured.
CYUSB3035 document number: 001-84160 rev. *b page 7 of 50 accessed as indicated by the p- port dma transfer register and the transfer size is determined by the p-port dma transfer size register. application processors with a dm a controller that use address auto-increment during dma transfers, can override this by connecting any higher-order address line (such as a[15]/a[23]/a[31]) of the applicat ion processor to fx3s?s a[7]. in the asynchronous sram mode, when reading from a buffer memory, fx3s supports two methods of reading out next data from the buffer. the next data ma y be read out on the rising edge of oe# or by toggling the leas t significant address bit a[0]. in this mode, the p-port interface works with a 32.5-ns minimum access cycle providing an interf ace data rate of up to 61.5 mb per second. figure 7. asynchronous sram interface asynchronous address/data multiplexed the physical admux memory interface consists of signals shown in figure 8 . this interface supports processors that implement a multiplexed address/data bus. figure 8. admux memory interface fx3s?s admux interface supports a 16-bit time-multiplexed address/data sram bus. for read operations, assert both ce# and oe#. for write operations, assert bot h ce# and we#. oe# is "don't care" during a write operation (during both address and data phase of the write cycle). the input data is latched on the rising edge of we# or ce#, whichever occurs first. latch the addresses prior to the write operation by toggling address valid (adv#). assert address valid (adv#) during the address phase of the write operation, as shown in figure 19 on page 28. adv# must be low during the address phase of a read/write operation. adv# must be high during the data phase of a read/write operation, as shown in figure 18 and figure 19 on page 28. synchronous admux interface fx3s's p-port supports a synchronous address/data multiplexed interface. this operat es at an interface frequency of up to 100 mhz and supports a 16-bit data bus. the rdy output signal from the fx3s device indicates a data valid for read transfers and is acknowledged for write transfers. figure 9. synchronous admux interface see the synchronous admux interface timing diagrams for details. processor mmc (pmmc) slave interface fx3s supports an mmc slave interface on the p-port. this interface is named "pmmc" to dist inguish it from the s-port mmc interface. figure 10 illustrates the signals used to connect to the host processor. the pmmc interface's go_irq_state command allows fx3s to communicate asynchronous events without requiring the int# signal. the use of the int# signal is optional. figure 10. pmmc interface configuration host processor west bridge benicia ce# a[7:0] dq[15:0] we# oe# fx3s host processor west bridge benicia ce# adv# a[7:0]/dq[15:0] we# oe# fx3s host processor west bridge benicia clk ce# adv# a[0:7]/dq[0:15] we# oe# rdy fx3s host processor west bridge benicia clk cmd dat[7:0] int# mmc4.2 host pmmc i/f fx3s
CYUSB3035 document number: 001-84160 rev. *b page 8 of 50 the mmc slave interface features are as follows: interface operations are comp atible with the mmc-system specification, mmca technica l committee, version 4.2. supports booting from an emmc device connected to the s-port. this feature is supported for emmc devices operating up to 52-mhz sdr. supports pmmc interface voltage ranges of 1.7 v to 1.95 v and 2.7 v to 3.6 v. supports open drain (both drive and receive open drain signals) on cmd pin to allow go_irq_state (cmd40) for pmmc. interface clock-frequency range: 0 to 52 mhz. supports 1-bit, 4-bit, or 8-bit mode of operation. this configuration is determined by the mmc initialization procedure. fx3s responds to standard init ialization phase commands as specified for the mmc 4.2 slave device. pmmc mode mmc 4.2 command classes: class 0 (basic), class 2 (block read), and class 4 (block write), class 9 (i/o). fx3s supports the following pmmc commands: class 0: basic cmd0, cmd1, cmd2, cmd3, cmd4, cmd6, cmd7, cmd8, cmd9, cmd10, cmd12, cmd 13, cmd15, cmd19, cmd5 (wakeup support) class 2: block read cmd16, cmd17, cmd18, cmd23 class 4: block write cmd16, cmd23, cmd24, cmd25 class 9: i-o cmd39, cmd40 cpu fx3s has an on-chip 32-bit, 200-mhz arm926ej-s core cpu. the core has direct access to 16 kb of instruction tightly coupled memory (tcm) and 8 kb of data tcm. the arm926ej-s core provides a jtag interface for firmware debugging. fx3s offers the following advantages: integrates 512 kb of embedded sram for code and data and 8 kb of instruction cache and data cache. implements efficient and flexible dma connectivity between the various peripherals (such as, usb, gpif ii, i 2 s, spi, uart), requiring firmware only to configure data accesses between peripherals, which are then managed by the dma fabric. allows easy application development on industry-standard development tools for arm926ej-s. examples of the fx3s firmware are available with the cypress ez-usb fx3s development kit. software apis that can be ported to an external processor are available with the cypress ez-usb fx3s software development kit. storage port (s-port) fx3s has two independent storage ports (s0-port and s1-port). both storage ports support t he following specifications: mmc-system specification, mm ca technical committee, version 4.41 sd specification, version 3.0 sdio host controller compliant with sdio specification version 2.00 (jan.30, 2007) both storage ports support the following features: sd/mmc clock stop fx3s supports the stop clock feature, which can save power if the internal buffer is full when receiving data from the sd/mmc/sdio. sd_clk output clock stop during the data transfer, the sd_clk clock can be enabled (on) or disabled (stopped) at any time by the internal flow control mechanism. sd_clk output frequency is dynamically configurable using a clock divisor from a system clock. the clock choice for the divisor is user-configurable through a register. for example, the following frequencies may be configured: 400 khz ? for the sd/mmc card initialization 20 mhz ? for a card with 0- to 20-mhz frequency 24 mhz ? for a card with 0- to 26-mhz frequency 48 mhz ? for a card with 0- to 52-mhz frequency (48-mhz frequency on sd_clk is supported when the clock input to fx3s is 19.2 mhz or 38.4 mhz) 52 mhz ? for a card with 0- to 52-mhz frequency (52-mhz frequency on sd_clk is supported when the clock input to fx3s is 26 mhz or 52 mhz) 100 mhz ? for a card with 0- to 100-mhz frequency if the ddr mode is selected, data is clocked on both the rising and falling ed ge of the sd clock. ddr clocks run up to 52 mhz. card insertion and removal detection fx3s supports the two-card insertion and removal detection mechanisms. use of sd_d[3] data: during system design, this signal must have an external 470-k pull-down resistor connected to sd_d[3]. sd cards have an internal 10-k pull-up resistor. when the card is inserted or removed from the sd/mmc connector, the voltage level at the sd_d[3] pin changes and triggers an interrupt to the cpu. the older generations of mmc cards do not support this card detection mechanism. use of the s0/s1_ins pin: some sd/mmc connectors facilitate a micro switch for card inserti on/removal detection. this micro switch can be connected to s0 /s1_ins. when the card is inserted or removed from the sd/mmc connector, it turns the micro switch on and off. this changes the voltage level at the pin that triggers the interrupt to the cpu. the card-detect micro switch polarity is assumed to be the same as the write-protect
CYUSB3035 document number: 001-84160 rev. *b page 9 of 50 micro switch polarity. a low indica tes that the card is inserted. this s0/s1_ins pin is shared between the two s-ports. register configuration determines which port gets to use this pin. this pin is mapped to the s1vddq power domain; if s0vddq and s1vddq are at diff erent voltage levels, this pin cannot be used as s1_ins. write protection (wp) the s0_wp/s1_wp (sd write protec tion) on s-port is used to connect to the wp micro switch of sd/mmc card connector. this pin internally connects to a cpu-accessible gpio for firmware to detect the sd card write protection. sdio interrupt the sdio interrupt functionality is supported as specified in the sdio specification version 2.00 (january 30, 2007). sdio read-wait feature fx3s supports the optional read-wait and suspend-resume features as defined in the sd io specification version 2.00 (january 30, 2007). jtag interface fx3s?s jtag interface has a standard five-pin interface to connect to a jtag debugger in order to debug firmware through the cpu-core's on-chip-debug circuitry. industry-standard debugging tools for the arm926ej-s core can be used for the fx3s application development. other interfaces fx3s supports the following serial peripherals: uart i 2 c i 2 s spi the spi, uart, and i 2 s interfaces are multiplexed on the serial peripheral port. uart interface the uart interface of fx3s supports full-duplex communication. it includes the signals noted in ta b l e 1 . the uart is capable of generat ing a range of baud rates, from 300 bps to 4608 kbps, selectable by the firmware. if flow control is enabled, then fx3s's uart only transmits data when the cts input is asserted. in addition to this, fx3s's uart asserts the rts output signal, when it is ready to receive data. i 2 c interface fx3s?s i 2 c interface is compatible with the i 2 c bus specification revision 3. this i 2 c interface is capable of operating only as i 2 c master; therefore, it may be us ed to communicate with other i 2 c slave devices. for example, fx3s may boot from an eeprom connected to the i 2 c interface, as a selectable boot option. fx3s?s i 2 c master controller also supports multi-master mode functionality. the power supply for the i 2 c interface is vio5, which is a separate power domain from the other serial peripherals. this gives the i 2 c interface the flexibility to operate at a different voltage than the other serial interfaces. the i 2 c controller supports bus frequencies of 100 khz, 400 khz, and 1 mhz. when vio5 is 1.2 v, the maximum operating frequency supported is 100 khz. when vio5 is 1.8 v, 2.5 v, or 3.3 v, the operating frequencies supported are 400 khz and 1 mhz. the i 2 c controller supports the clock-stretching feature to enable slower devices to exercise flow control. the i 2 c interface?s scl and sda signals require external pull-up resistors. the pull-up resistors must be connected to vio5. i 2 s interface fx3s has an i 2 s port to support external audio codec devices. fx3s functions as i 2 s master as transmitter only. the i 2 s interface consists of four signa ls: clock line (i2s_clk), serial data line (i2s_sd), word select line (i2s_ws), and master system clock (i2s_mclk). fx3s can generate the system clock as an output on i2s_mclk or a ccept an external system clock input on i2s_mclk. the sampling frequencies supported by the i 2 s interface are 32 khz, 44.1 khz, and 48 khz. spi interface fx3s supports an spi master interface on the serial peripherals port. the maximum operation frequency is 33 mhz. the spi controller supports four modes of spi communication (see spi timing specification on page 44 for details on the modes) with the start-stop clock. this controller is a single-master controller with a si ngle automated ssn control. it supports transaction sizes ranging from 4 bits to 32 bits. table 1. uart interface signals signal description tx output signal rx input signal cts flow control rts flow control
CYUSB3035 document number: 001-84160 rev. *b page 10 of 50 boot options fx3s can load boot images from various sources, selected by the configuration of the pmod e pins. following are the fx3s boot options: boot from usb boot from i 2 c boot from spi (spi devices supported are m25p16 (16 mbit), m25p80 (8 mbit), and m25p40 (4 mbit)) or their equivalents boot from emmc (s0-port) boot from gpif ii async admux mode boot from gpif ii sync admux mode boot from gpif ii async sram mode boot from pmmc (p-port) reset hard reset a hard reset is initiated by asserting the reset# pin on fx3s. the specific reset sequence and timing requirements are detailed in figure 31 on page 46 and table 19 on page 45. all i/os are tristated during a hard reset. soft reset in a soft reset, the processor sets the appropriate bits in the pp_init control register. there are two types of soft reset: cpu reset ? the cpu program counter is reset. firmware does not need to be reloaded following a cpu reset. whole device reset ? this reset is identical to hard reset. the firmware must be reloaded following a whole device reset. clocking fx3s allows either a crystal to be connected between the xtalin and xtalout pins or an external clock to be connected at the clkin pin. the xtalin, xtalout, clkin, and clkin_32 pins can be left unconnected if they are not used. crystal frequency supported is 19.2 mhz, while the external clock frequencies supported ar e 19.2, 26, 38.4, and 52 mhz. fx3s has an on-chip oscillator circuit that uses an external 19.2-mhz (100 ppm) crystal (when the crystal option is used). an appropriate load capacitance is required with a crystal. refer to the specification of the crystal used to determine the appro- priate load capacitance. the fslc[2:0] pins must be configured appropriately to select the crystal- or clock-frequency option. the configuration options are shown in ta b l e 3 . clock inputs to fx3s must me et the phase noise and jitter requirements specified in table 4 on page 11. the input clock frequency is independent of the clock and data rate of the fx3s core or any of the device interfaces (including p-port and s-port). the internal pll applies the appropriate clock multiply option depending on the input frequency. table 2. fx3s booting options pmode[2:0] [2] boot from f00 sync admux (16-bit) f01 async admux (16-bit) f10 pmmc legacy f11 usb boot f0f async sram (16-bit) f1f i 2 c, on failure, usb boot is enabled 1ff i 2 c only 0f1 spi, on failure, usb boot is enabled 000 s0-port (emmc) on failure, usb boot is enabled 100 s0-port (emmc) note 2. f indicates floating. table 3. crystal/clock frequency selection fslc[2] fslc[1] fslc[0] crystal/clock frequency 0 0 0 19.2-mhz crystal 1 0 0 19.2-mhz input clk 1 0 1 26-mhz input clk 1 1 0 38.4-mhz input clk 1 1 1 52-mhz input clk
CYUSB3035 document number: 001-84160 rev. *b page 11 of 50 32-khz watchdog timer clock input fx3s includes a watchdog timer. the watchdog timer can be used to interrupt the arm926ej- s core, automatically wake up the fx3s in standby mode, and reset the arm926ej-s core. the watchdog timer runs a 32-khz clock, which may be optionally supplied from an exte rnal source on a dedicated fx3s pin. the firmware can disable the watchdog timer. requirements for the optional 32-khz clock input are listed in ta b l e 5 . power fx3s has the following power supply domains: io_vddq : this is a group of independent supply domains for digital i/os. the voltage level on these supplies is 1.8 v to 3.3 v. fx3s provides six independent supply domains for digital i/os listed as follows (see pin description on page 16 for details on each of the power domain signals): ? vio1: gpif ii i/o ? vio2: s0-port supply ? vio3: s1-port supply ? vio4: s1-port and low speed peripherals (uart/spi/i2s) supply ? vio5: i 2 c and jtag (supports 1.2 v to 3.3 v) ? cvddq: clock ? v dd : this is the supply voltage for the logic core. the nominal supply-voltage level is 1.2 v. this supplies the core logic circuits. the same supply must also be used for the following: ? avdd: this is the 1.2-v supply for the pll, crystal oscilla- tor, and other core analog circuits ? u3txvddq/u3rxvddq: these are the 1.2-v supply volt- ages for the usb 3.0 interface. vbatt/vbus: this is the 3.2-v to 6-v battery power supply for the usb i/o and analog circuits. this supply powers the usb transceiver through fx3s's internal voltage regulator. vbatt is internally regulated to 3.3 v. table 4. fx3s input clock specifications parameter description specification units min max phase noise 100-hz offset ? ?75 db 1- khz offset ? ?104 db 10-khz offset ? ?120 db 100-khz offset ? ?128 db 1-mhz offset ? ?130 db maximum frequency deviation ? 150 ppm duty cycle 30 70 % overshoot ? 3 % undershoot ? ?3 % rise time/fall time ? 3 ns table 5. 32-khz clock input requirements parameter min max units duty cycle 40 60 % frequency deviation ? 200 ppm rise time/fall time ? 200 ns
CYUSB3035 document number: 001-84160 rev. *b page 12 of 50 power modes fx3s supports the following power modes: normal mode: this is the full-functional operating mode. the internal cpu clock and the internal plls are enabled in this mode. ? normal operating power consumption does not exceed the sum of i cc core max and i cc usb max (see ta b l e 7 for current consumptio n specifications). ? the i/o power supplies vio2, vio3, vio4, and vio5 can be turned off when the corresponding interface is not in use. vio1 cannot be turned off at any time if the gpif ii interface is used in the application. low-power modes (see ta b l e 6 on page 12): ? suspend mode with usb 3.0 phy enabled (l1) ? suspend mode with usb 3.0 phy disabled (l2) ? standby mode (l3) ? core power-down mode (l4) table 6. entry and exit methods for low-power modes low-power mode characteristics methods of entry methods of exit suspend mode with usb 3.0 phy enabled (l1) the power consumption in this mode does not exceed isb 1 usb 3.0 phy is enabled and is in u3 mode (one of the suspend modes defined by the usb 3.0 specification). this one block alone is operational with its internal clock while all other clocks are shut down all i/os maintain their previous state power supply for the wakeup source and core power must be retained. all other power domains can be turned on/off individually the states of the conf iguration registers, buffer memory, and all internal ram are maintained all transactions must be completed before fx3s enters suspend mode (state of outstanding transactions are not preserved) the firmware resumes operation from where it was suspended (except when woken up by reset# assertion) because the program counter does not reset firmware executing on arm926ej-s core can put fx3s into suspend mode. for example, on usb suspend condition, firmware may decide to put fx3s into suspend mode external processor, through the use of mailbox registers, can put fx3s into suspend mode d+ transitioning to low or high d- transitioning to low or high impedance change on otg_id pin resume condition on ssrx detection of vbus level detect on uart_cts (program- mable polarity) gpif ii interface assertion of ctl[0] assertion of reset#
CYUSB3035 document number: 001-84160 rev. *b page 13 of 50 suspend mode with usb 3.0 phy disabled (l2) the power consumption in this mode does not exceed isb 2 usb 3.0 phy is disabled and the usb interface is in suspend mode the clocks are shut off. the plls are disabled all i/os maintain their previous state usb interface maintains the previous state power supply for the wakeup source and core power must be retained. all other power domains can be turned on/off individually the states of the conf iguration registers, buffer memory and all internal ram are maintained all transactions must be completed before fx3s enters suspend mode (state of outstanding transactions are not preserved) the firmware resumes operation from where it was suspended (except when woken up by reset# assertion) because the program counter does not reset firmware executing on arm926ej-s core can put fx3s into suspend mode. for example, on usb suspend condition, firmware may decide to put fx3s into suspend mode external processor, through the use of mailbox registers can put fx3s into suspend mode d+ transitioning to low or high d- transitioning to low or high impedance change on otg_id pin resume condition on ssrx detection of vbus level detect on uart_cts (program- mable polarity) gpif ii interface assertion of ctl[0] assertion of reset# standby mode (l3) the power consumption in this mode does not exceed isb3 all configuration register settings and program/data ram contents are preserved. however, data in the buffers or other parts of the data path, if any, is not guaranteed. theref ore, the external processor should take care that the data needed is read before putting fx3s into this standby mode the program counter is reset after waking up from standby gpio pins maintain their configuration crystal oscillator is turned off internal pll is turned off usb transceiver is turned off arm926ej-s core is powered down. upon wakeup, the core re-starts and runs the program stored in the program/data ram power supply for the wakeup source and core power must be retained. all other power domains can be turned on/off individually firmware executing on arm926ej-s core or external processor configures the appropriate register detection of vbus level detect on uart_cts (program- mable polarity) gpif ii interface assertion of ctl[0] assertion of reset# table 6. entry and exit methods for low-power modes (continued) low-power mode characteristics methods of entry methods of exit
CYUSB3035 document number: 001-84160 rev. *b page 14 of 50 core power down mode (l4) the power consumption in this mode does not exceed isb 4 core power is turned off all buffer memory, configuration registers, and the program ram do not maintain state. after exiting this mode, reload the firmware in this mode, all other power domains can be turned on/off individually turn off v dd reapply vdd assertion of reset# table 6. entry and exit methods for low-power modes (continued) low-power mode characteristics methods of entry methods of exit
CYUSB3035 document number: 001-84160 rev. *b page 15 of 50 configuration options configuration options are availa ble for specific usage models. contact cypress applications or marketing for details. digital i/os fx3s has internal firmware-controlled pull-up or pull-down resistors on all digital i/o pins. an internal 50-k resistor pulls the pins high, while an internal 10-k resistor pulls the pins low to prevent them from floating. the i/o pins may have the following states: tristated (high-z) weak pull-up (via internal 50 k ) pull-down (via internal 10 k ) hold (i/o hold its value) when in low-power modes the jtag tdi, tmc, and trst# signals have fixed 50-k internal pull-ups, and the tck signal has a fixed 10-k pull-down resistor. all unused i/os should be pulled high by using the internal pull-up resistors. all unused outputs should be left floating. all i/os can be driven at full-strength, three-quarter strength, half-strength, or quarter-stren gth. these drive strengths are configured separately for each interface. gpios ez-usb enables a flexible pin configuration both on the gpif ii and the serial peripheral interfaces. any unused control pins (except ctl[15]) on the gpif ii interface can be used as gpios. similarly, any unused pins on the serial peripheral interfaces may be configured as gpios. see the pin description on page 16 for pin configuration options. all gpif ii and gpio pins support an external load of up to 16 pf for every pin. emi fx3s meets emi requirements outlined by fcc 15b (usa) and en55022 (europe) for consumer electronics. fx3s can tolerate reasonable emi, conducted by the aggressor, outlined by these specifications and continue to function as expected. system-level esd fx3s has built-in esd protection on the d+, d?, and gnd pins on the usb interface. the esd protection levels provided on these ports are: 2.2-kv human body model (hbm) based on jesd22-a114 specification 6-kv contact discharge and 8-kv air gap discharge based on iec61000-4-2 level 3a 8-kv contact discharge and 15-kv air gap discharge based on iec61000-4-2 level 4c. this protection ensures the device continues to function after esd events up to the levels stated in this section. the ssrx+, ssrx?, sstx+, and ss tx? pins only have up to 2.2-kv hbm internal esd protection. figure 11. fx3s ball map (top view) 12 34567891011 a u3vssq u3rxvddq ssrxm ssrxp sstxp sstxm avdd vss dp dm nc b vio4 fslc[0] r_usb3 fslc[1] u3txvddq cvddq avss vss vss vdd trst# c gpio[54] gpio[55] vdd gpio[57] reset# xtalin xtalout r_usb2 otg_id tdo vio5 d gpio[ 50] gpio[ 51] gpio[ 52] gpio[ 53] gpio[ 56] clkin_32 clkin vss i2c_gpio[ 58] i2c_gpio[ 59] o[ 6 0] e gpio[ 4 7] vss vio3 gpio[49] gpio[48] fslc[2] tdi tms vdd vbatt vbus f v io2 gpio[ 45] gpio[ 4 4 ] gpio[ 4 1] gpio[ 4 6] tck gpio[ 2 ] gpio[ 5] gpio[ 1] gpio[ 0 ] v dd g vss gpio[ 4 2] gpio[ 4 3 ] gpio[ 3 0 ] gpio[ 2 5] gpio[ 2 2] gpio[ 2 1] gpio[ 15] gpio[ 4] gpio[ 3 ] vss h v dd gpio[ 3 9] gpio[ 4 0 ] gpio[ 3 1] gpio[ 2 9] gpio[ 2 6] gpio[ 2 0 ] gpio[ 2 4] gpio[ 7] gpio[ 6 ] v io1 j gpio[ 3 8 ] gpio[ 3 6] gpio[ 3 7] gpio[ 3 4 ] gpio[ 2 8] gpio[ 16] gpio[ 19 ] gpio[ 14] gpio[ 9] gpio[ 8 ] v dd k gpio[ 35] gpio[ 33] vss vss gpio[27] gpio[23] gpio[18] gpio[17] gpio[13] gpio[12] gpio[10] l vss vss vss gpio[32] vdd vss vdd int# vio1 gpio[11] vss
CYUSB3035 document number: 001-84160 rev. *b page 16 of 50 pin description fx3s pin description pin power domain i/o name p-port gpif ii interface slave fifo interface pmmc async sram async admux syncadmux f10 vio1 i/o gpio[0] dq[0] dq[0] mmc_d0 dq[0] dq[0]/a[0] dq[0]/a[0] f9 vio1 i/o gpio[1] dq[1] dq[1] mmc_d1 dq[1] dq[1]/a[1] dq[1]/a[1] f7 vio1 i/o gpio[2] dq[2] dq[2] mmc_d2 dq[2] dq[2]/a[2] dq[2]/a[2] g10 vio1 i/o gpio[3] dq[3] dq[3] mmc_d3 dq[3] dq[3]/a[3] dq[3]/a[3] g9 vio1 i/o gpio[4] dq[4] dq[4] mmc_d4 dq[4] dq[4]/a[4] dq[4]/a[4] f8 vio1 i/o gpio[5] dq[5] dq[5] mmc_d5 dq[5] dq[5]/a[5] dq[5]/a[5] h10 vio1 i/o gpio[6] dq[6] dq[6] mmc_d6 dq[6 ] dq[6]/a[6] dq[6]/a[6] h9 vio1 i/o gpio[7] dq[7] dq[7] mmc_d7 dq[7 ] dq[7]/a[7] dq[7]/a[7] j10 vio1 i/o gpio[8] dq[8] dq[8] gpio dq[8 ] dq[8]/a[8] dq[8]/a[8] j9 vio1 i/o gpio[9] dq[9] dq[9] gpio dq[9 ] dq[9]/a[9] dq[9]/a[9] k11 vio1 i/o gpio[10] dq[10] dq[10] gpio dq[10] dq[10]/a[10] dq[10]/a[10] l10 vio1 i/o gpio[11] dq[11] dq[11] gpio dq[11] dq[11]/a[11] dq[11]/a[11] k10 vio1 i/o gpio[12] dq[12] dq[12] gpio dq[12] dq[12]/a[12] dq[12]/a[12] k9 vio1 i/o gpio[13] dq[13] dq[13] gpio dq[13] dq[13]/a[13] dq[13]/a[13] j8 vio1 i/o gpio[14] dq[14] dq[14] gpio dq[14] dq[14]/a[14] dq[14]/a[14] g8 vio1 i/o gpio[15] dq[15] dq[15] gpio dq[15] dq[15]/a[15] dq[15]/a[15] j6 vio1 i/o gpio[16] pclk clk mmc_clk clk clk clk k8 vio1 i/o gpio[17] ctl[0] slcs# gpio ce# ce# ce# k7 vio1 i/o gpio[18] ctl[1] slwr# mmc_cmd we# we# we# j7 vio1 i/o gpio[19] ctl[2] sloe# gpio oe# oe# oe# h7 vio1 i/o gpio[20] ctl[3] slrd# gpio dack# dack# dack# g7 vio1 i/o gpio[21] ctl[4] flaga gpio drq# drq# drq# g6 vio1 i/o gpio[22] ctl[5] flagb gpio a[7] gpio gpio k6 vio1 i/o gpio[23] ctl[6] gpio gpio a[6] gpio rdy h8 vio1 i/o gpio[24] ctl[7] pktend# gpio a[5] gpio gpio g5 vio1 i/o gpio[25] ctl[8] gpio gpio a[4] gpio gpio h6 vio1 i/o gpio[26] ctl[9] gpio gpio a[3] gpio gpio k5 vio1 i/o gpio[27] ctl[10] gpio gpio a[2] adv# adv# j5 vio1 i/o gpio[28] ctl[11] a1 carkit_uart _rx a[1] gpio gpio h5 vio1 i/o gpio[29] ctl[12] a0 carkit_uart _tx a[0] gpio gpio g4 vio1 i/o gpio[30] pmode[0] pmode[0] pmode[0] pmode[0] pmode[0] pmode[0] h4 vio1 i/o gpio[31] pmode[1] pmode[1] pmode[1] pmode[1] pmode[1] pmode[1] l4 vio1 i/o gpio[32] pmode[2] pmode[2] pmode[2] pmode[2] pmode[2] pmode[2] l8 vio1 i/o int# int#/ctl[15] ctl[15] int# int# int# int# c5 cvddq i reset# reset# reset# reset# reset# reset# reset#
CYUSB3035 document number: 001-84160 rev. *b page 17 of 50 fx3s pin description pin power domain i/o name s0-port 8b mmc sd+gpio gpio k2 vio2 i/o gpio[33] s0_sd0 s0_sd0 gpio j4 vio2 i/o gpio[34] s0_sd1 s0_sd1 gpio k1 vio2 i/o gpio[35] s0_sd2 s0_sd2 gpio j2 vio2 i/o gpio[36] s0_sd3 s0_sd3 gpio j3 vio2 i/o gpio[37] s0_sd4 gpio gpio j1 vio2 i/o gpio[38] s0_sd5 gpio gpio h2 vio2 i/o gpio[39] s0_sd6 gpio gpio h3 vio2 i/o gpio[40] s0_sd7 gpio gpio f4 vio2 i/o gpio[41] s0_cmd s0_cmd gpio g2 vio2 i/o gpio[42] s0_clk s0_clk gpio g3 vio2 i/o gpio[43] s0_wp s0_wp gpio f3 vio2 i/o gpio[44] s0s1_ins s0s1_ins gpio f2 vio2 i/o gpio[45] mmc0_rst_out gpio gpio s1-port 8b mmc sd+uart sd+spi sd+gpio gpio gpio+uart +i2s sd+i2s uart+spi +i2s f5 vio3 i/o gpio[46] s1_sd0 s1_sd0 s1_s d0 s1_sd0 gpio gpio s1_sd0 uart_rt s e1 vio3 i/o gpio[47] s1_sd1 s1_sd1 s1_s d1 s1_sd1 gpio gpio s1_sd1 uart_ct s e5 vio3 i/o gpio[48] s1 _sd2 s1_sd2 s1_sd2 s1_sd2 gpio gpio s1_sd2 uart_tx e4 vio3 i/o gpio[49] s1 _sd3 s1_sd3 s1_sd3 s1_sd3 gpio gpio s1_sd3 uart_rx d1 vio3 i/o gpio[50] s1_cmd s1_cmd s 1_cmd s1_cmd gpio i2 s_clk s1_cmd i2s_clk d2 vio3 i/o gpio[51] s1_clk s1_clk s1 _clk s1_clk gpio i2 s_sd s1_clk i2s_sd d3 vio3 i/o gpio[52] s1_wp s1_wp s1_wp s1_wp gpio i2s_ws s1_wp i2s_ws d4 vio4 i/o gpio[53] s1_sd4 uart_rts spi_sck gpio gpio uart_rts gpio spi_sck c1 vio4 i/o gpio[54] s1_sd5 uart_cts spi_ssn gpio gpio ua rt_cts i2s_clk spi_ssn c2 vio4 i/o gpio[55] s1_sd6 uart_tx spi_miso gpio gpio uart_tx i2s_sd spi_miso d5 vio4 i/o gpio[56] s1_sd7 uart_rx spi_mosi gpio gpio uart_rx i2s_ws spi_mosi c4 vio4 i/o gpio[57] mmc1_r s t_out gpio gpio gpio gpio i2s_mclk i2s_mclk i2s_mclk
CYUSB3035 document number: 001-84160 rev. *b page 18 of 50 fx3s pin description pin power domain i/o name usb port c9 vbus/ vbatt i otg_id otg_id a3 u3rx vddq i ssrxm ssrx- a4 u3rx vddq i ssrxp ssrx+ a6 u3tx vddq o sstxm sstx- a5 u3tx vddq o sstxp sstx+ a9 vbus/ vbatt i/o dp d+ a10 vbus/ vbatt i/o dm d? a11 nc no connect crystal/clocks b2 cvddq i fslc[0] fslc[0] c6 avdd i/o xtalin xtalin c7 avdd i/o xtalout xtalout b4 cvddq i fslc[1] fslc[1] e6 cvddq i fslc[2] fslc[2] d7 cvddq i clkin clkin d6 cvddq i clkin_32 clkin_32 i2c and jtag d9 vio5 i/o i2c_gpio[5 8] i2c_scl d10 vio5 i/o i2c_gpio[5 9] i2c_sda e7 vio5 i tdi tdi c10 vio5 o tdo tdo b11 vio5 i trst# trst# e8 vio5 i tms tms f6 vio5 i tck tck d11 vio5 o o[60] charger detect output
CYUSB3035 document number: 001-84160 rev. *b page 19 of 50 fx3s pin description pin power domain i/o name power e10 pwr vbatt b10 pwr vdd a1 pwr u3vssq e11 pwr vbus d8 pwr vss h11 pwr vio1 e2 pwr vss l9 pwr vio1 g1 pwr vss f1 pwr vio2 g11 pwr vss e3 pwr vio3 l1 pwr vss b1 pwr vio4 l6 pwr vss b6 pwr cvddq b5 pwr u3txvddq a2 pwr u3rxvddq c11 pwr vio5 l11 pwr vss a7 pwr avdd b7 pwr avss c3 pwr vdd b8 pwr vss e9 pwr vdd b9 pwr vss f11 pwr vdd h1 pwr vdd l7 pwr vdd j11 pwr vdd l5 pwr vdd k4 pwr vss l3 pwr vss k3 pwr vss l2 pwr vss a8 pwr vss precision resistors c8 vbus/ vbatt i/o r_usb2 precision resistor for usb 2.0 (connect a 6.04 k ? 1% resistor between this pin and gnd) b3 u3tx vddq i/o r_usb3 precision resistor for usb 3.0 (connect a 200 ? 1% resistor between this pin and gnd)
CYUSB3035 document number: 001-84160 rev. *b page 20 of 50 absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. storage temperature............................... ...... ?65 c to +150 c ambient temperature with power supplied (industrial)............. ....... ... ...... ?40 c to +85 c supply voltage to ground potential v dd , a vddq ......................................................................1.25 v v io1 ,v io2 , v io3 , v io4 , v io5 ........................ ...................... ...3.6 v u3tx vddq , u3rx vddq ......................................... ...........1.25 v dc input voltage to any input pin. ............ ................ .....vcc+0.3 dc voltage applied to outputs in high z state.................... ..............................vcc+0.3 (vcc is the corresponding i/o voltage) static discharge voltage esd protection levels: 2.2-kv hbm based on jesd22-a114 additional esd protection levels on d+, d?, and gnd pins, and serial peripheral pins 6-kv contact discharge, 8-kv air gap discharge based on iec61000-4-2 level 3a, 8-kv contact discharge, and 15-kv air gap discharge based on iec61000-4-2 level 4c latch-up current............................ ....................... .......> 200 ma maximum output short-circuit current for all i/o configurations. (vout = 0v).................... ..... ?100 ma operating conditions t a (ambient temperature under bias) industrial....................................................... .. ?40 c to +85 c v dd , a vddq , u3tx vddq , u3rx vddq supply voltage................................................ ...1.15 v to 1.25 v v batt supply voltage.......................... ......................3.2 v to 6 v v io1 , v io2 , v io3 , v io4 , c vddq supply voltage.................................................... ...1.7 v to 3.6 v v io5 supply voltage...................... ...................... 1.15 v to 3.6 v table 7. dc specifications parameter description min max units notes v dd core voltage supply 1.15 1.25 v 1.2-v typical a vdd analog voltage supply 1.15 1.25 v 1.2-v typical v io1 gpif ii i/o power supply domain 1.7 3.6 v 1.8-, 2.5-, and 3.3-v typical v io2 s0-port power supply domain 1.7 3.6 v 1.8-, 2.5-, and 3.3-v typical v io3 s1-port power supply domain 1.7 3.6 v 1.8-, 2.5-, and 3.3-v typical v io4 s1-port and uart/spi/i2s power supply domain 1.7 3.6 v 1.8-, 2.5-, and 3.3-v typical v batt usb voltage supply 3.2 6 v 3.7-v typical v bus usb voltage supply 4.0 6 v 5-v typical u3tx vddq usb 3.0 1.2-v supply 1.15 1.25 v 1.2-v typical. a 22-f bypass capacitor is required on this power supply. u3rx vddq usb 3.0 1.2-v supply 1.15 1.25 v 1.2-v typical. a 22-f bypass capacitor is required on this power supply. c vddq clock voltage supply 1.7 3.6 v 1.8-, 3.3-v typical v io5 i 2 c and jtag voltage supply 1.15 3. 6 v 1.2-, 1.8-, 2.5-, and 3.3-v typical v ih1 input high voltage 1 0.625 vcc vcc + 0.3 v for 2.0 v v cc 3.6 v (except usb port).vcc is the corresponding i/o voltage supply. v ih2 input high voltage 2 vcc ? 0.4 vcc + 0.3 v for 1.7 v v cc 2.0 v (except usb port).vcc is the corresponding i/o voltage supply. v il input low voltage ?0.3 0.25 vcc v vcc is the corresponding i/o voltage supply.
CYUSB3035 document number: 001-84160 rev. *b page 21 of 50 v oh output high voltage 0.9 vcc ? v i oh (max) = ?100 a tested at quarter drive st rength. vcc is the corresponding i/o voltage supply. v ol output low voltage ? 0.1 vcc v i ol (min) = +100 a tested at quarter drive st rength. vcc is the corresponding i/o voltage supply. i ix input leakage current for all pins except sstxp/ssxm/ssrxp/ssrxm ?1 1 a all i/o signals held at v ddq (for i/os with a pull-up or pull-down resistor connected, the leakage current increases by v ddq /r pu or v ddq /r pd i oz output high-z leakage current for all pins except sstxp/ ssxm/ ssrxp/ssrxm ?1 1 a all i/o signals held at v ddq i cc core core and analog voltage operating current ? 200 ma total current through a vdd , v dd i cc usb usb voltage supply operating current ? 60 ma i sb1 total suspend current during suspend mode with usb 3.0 phy enabled (l1) ? ? ma core current: 1.5 ma i/o current: 20 a usb current: 2 ma for typical pvt (typical silicon, all power supplies at their respective nominal levels at 25 c.) i sb2 total suspend current during suspend mode with usb 3.0 phy disabled (l2) ? ? ma core current: 250 a i/o current: 20 a usb current: 1.2 ma for typical pvt (typical silicon, all power supplies at their respective nominal levels at 25 c.) i sb3 total standby current during standby mode (l3) ? ? a core current: 60 a i/o current: 20 a usb current: 40 a for typical pvt (typical silicon, all power supplies at their respective nominal levels at 25 c.) i sb4 total standby current during core power-down mode (l4) ? ? a core current: 0 a i/o current: 20 a usb current: 40 a for typical pvt (typical silicon, all power supplies at their respective nominal levels at 25 c.) v ramp voltage ramp rate on core and i/o supplies 0.2 50 v/ms voltage ramp must be monotonic v n noise level permitted on v dd and i/o supplies ? 100 mv max p-p noise level permitted on all supplies except a vdd v n_avdd noise level permitted on a vdd supply ? 20 mv max p-p noise level permitted on a vdd table 7. dc specifications (continued) parameter description min max units notes
CYUSB3035 document number: 001-84160 rev. *b page 22 of 50 ac timing parameters gpif ii timing figure 12. gpif ii timing in synchronous mode - ctl (out) ctl(in) ts th tdh tds tclk clk tctlo tcoe data (in) data1 (out) thz tlz tdoh tcoh tclkh tclkl tlz data2 (out) tco tdoh dq[15:0] note 3. all parameters guaranteed by design and validated through characterization. table 8. gpif ii timing parameters in synchronous mode [3] parameter description min max units frequency interface clock frequency ? 100 mhz tclk interface clock period 10 ? ns tclkh clock high time 4 ? ns tclkl clock low time 4 ? ns ts ctl input to clock setup time (sync speed = 1) 2?ns th ctl input to clock hold time (sync speed = 1) 0.5 ? ns tds data in to clock setup time (sync speed = 1) 2?ns tdh data in to clock hold time (sync speed = 1) 0.5 ? ns tco clock to data out propagation delay when dq bus is already in output direction (sync speed = 1) ?8ns tcoe clock to data out propagation delay when dq lines change to output from tristate and valid data is available on the dq bus (sync speed = 1) -9 tctlo clock to ctl out propagation delay (sync speed = 1) ? 8 ns tdoh clock to data out hold 2 ? ns tcoh clock to ctl out hold 0 ? ns thz clock to high-z ? 8 ns tlz clock to low-z (sync speed = 1) 0 ? ns ts_ss0 ctl input/data input to clock setup time (sync speed = 0) 5 ? ns th_ss0 ctl input/data input to clock hold time (sync speed = 0) 2.5 ? ns tco_ss0 clock to data out / ctl out propagation delay (sync speed = 0) ?15ns tlz_ss0 clock to low-z (sync speed = 0) 2 ? ns
CYUSB3035 document number: 001-84160 rev. *b page 23 of 50 figure 13. gpif ii timing in asynchronous mode figure 14. gpif ii timi ng in asynchronous ddr mode data/ addr ctl# (i/p , ale/ dle) tchz tctlalpha tctlbeta tdh/ tah tctldeassert_dqlatch tctldeassert data in tctlassert_dqlatch tchz/toehz tclz/ toelz tds/ tas data out data out ctl# (i/p, non ale/ dle alpha o/p beta o/p tctl# (o/p) tctlassert tctldeassert 11 1. n is an integer >= 0 taa/tdo tctlassert data/ addr ctl# i/p (non dle/ale) tdst tdht tctlassert_dqassert tctldeassert_dqassert data in ctl# (i/p) tds tctlassert_dqlatchddr tctldeassert_dqlatchddr tdh tds tdh
CYUSB3035 document number: 001-84160 rev. *b page 24 of 50 note 4. all parameters guaranteed by design and validated through characterization. table 9. gpif ii timing in asynchronous mode [4] note the following parameters assume one state transition parameter description min max units tds data in to dle setup time. valid in ddr async mode. 2.3 ? ns tdh data in to dle hold time. valid in ddr async mode. 2 ? ns tas address in to ale setup time 2.3 ? ns tah address in to ale hold time 2 ? ns tctlassert ctl i/o asse rted width for ctrl inputs without dq input association and for outputs. 7?ns tctldeassert ctl i/o deasserted width for ctrl inputs without dq input association and for outputs. 7?ns tctlassert_dqassert ctl asserted pulse width for ctl inputs that signify dq inputs valid at the asserting edge but do not employ in-built latches (ale/dle) for those dq inputs. 20 ? ns tctldeassert_dqassert ctl deasserted pulse width for ctl inputs that signify dq input valid at the asserting edge but do not employ in-built latches (ale/dle) for those dq inputs. 7?ns tctlassert_dqdeassert ctl asserted pulse width for ctl inputs that signify dq inputs valid at the deasserting edge but do not employ in-built latches (ale/dle) for those dq inputs. 7?ns tctldeassert_dqdeassert ctl deasserted pulse width for ctl inputs that signify dq inputs valid at the deasserting edge but do not employ in-built latches (ale/dle) for those dq inputs. 20 ? ns tctlassert_dqlatch ctl asserted pulse width for ctl inputs that employ in-built latches (ale/dle) to latch the dq inputs. in this non-ddr case, in-built latches are always close at the deasserting edge. 7?ns tctldeassert_dqlatch ctl deasserted pulse width for ctl inputs that employ in-built latches (ale/dle) to latch the dq inputs. in this non-ddr case, in-built latches always close at the deasserting edge. 10 ? ns tctlassert_dqlatchddr ctl asserted pulse width for ctl inputs that employ in-built latches (dle) to latch the dq inputs in ddr mode. 10 ? ns tctldeassert_dqlatchddr ctl deasserted pulse width for ctl inputs that employ in-built latches (dle) to latch the dq inputs in ddr mode. 10 ? ns taa dq/ctl input to dq output time when dq change or ctl change needs to be detected and affects internal updates of input and output dq lines. ?30ns tdo ctl to data out when the ctl change merely enables the output flop update whose data was already established. ?25ns toelz ctl designated as oe to low-z. time when external devices should stop driving data. 0?ns toehz ctl designated as oe to high-z 8 8 ns tclz ctl (non-oe) to low-z. time when external devices should stop driving data. 0?ns tchz ctl (non-oe) to high-z 30 30 ns tctlalpha ctl to alpha change at output ? 25 ns tctlbeta ctl to beta change at output ? 30 ns tdst addr/data setup when dle/ale not used 2 ? ns tdht addr/data hold when dle/ale not used 20 ? ns
CYUSB3035 document number: 001-84160 rev. *b page 25 of 50 asynchronous sram timing figure 15. non-multiplexed asynchronous sram read timing trc toe tolz t o h h address ce# oe# data out high impedance oe# controlled timing socket read ? address transition controlled timing (oe# is asserted) high impedance data valid data valid high impedance tohc taos t o e z we# (high) data out taa toh a[0] high impedance data valid data valid data valid oe# toe tah
CYUSB3035 document number: 001-84160 rev. *b page 26 of 50 figure 16. non-multiplexed asynchronous s ram write timing (we# and ce# controlled) write cycle 2 ce# controlled, oe# high during write twc tcw taw tas tah tds tdh twhz valid data address data i/o twp ce# we# oe# write cycle 1 we# controlled, oe# high during write twph valid data twc tcw taw tas tah tds tdh twhz valid data address data i/o twp ce# we# oe# tcph valid data
CYUSB3035 document number: 001-84160 rev. *b page 27 of 50 figure 17. non-multiplexed asynchronous sr am write timing (we# controlled, oe# low) twc tcw taw tas tah tds tdh valid data ce# we# data i/o twp tow twhz write cycle 3 we# controlled. oe# low note : twp must be adjusted such that twp > twhz + tds note 5. all parameters guaranteed by design and validated through characterization. table 10. asynchronous sram timing parameters [5] parameter description min max units sram interface bandwidth ? 61.5 mbps trc read cycle time 32.5 ? ns taa address to data valid ? 30 ns taos address to oe# low setup time 7 ? ns toh data output hold from address change 3 ? ns tohh oe# high hold time 7.5 ? ns tohc oe# high to ce# high 2 ? ns toe oe# low to data valid ? 25 ns tolz oe# low to low-z 0 ? ns twc write cycle time 30 ? ns tcw ce# low to write end 30 ? ns taw address valid to write end 30 ? ns tas address setup to write start 7 ? ns tah address hold time from ce# or we# 2 ? ns twp we# pulse width 20 ? ns twph we# high time 10 ? ns tcph ce# high time 10 ? ns tds data setup to write end 7 ? ns tdh data hold to write end 2 ? ns twhz write to dq high-z output ? 22.5 ns toez oe# high to dq high-z output ? 22.5 ns tow end of write to low-z output 0 ? ns
CYUSB3035 document number: 001-84160 rev. *b page 28 of 50 admux timing for asynchronous access figure 18. admux asynchronous random read figure 19. admux asynchronous random write valid address a[0:7]/dq[0:15] adv# oe# ce# valid data t v p tavs tavh tavoe t c o trc thz thz t o e tolz tceav note: 1. multiple read cycles can be executed while keeping ce# low. 2. read operation ends with either de-assertion of either oe# or ce#, whichever comes earlier. valid addr tacc we# (high) tcph address valid a[0:7]/dq[0:15] adv# we# ce# data valid tavwe twp tds tdh t v p tavs tavh tcw note: 1. multiple write cycles can be executed while keeping ce# low. 2. write operation ends with de-assertion of either we# or ce#, whichever comes earlier. tcph twc valid addr taw tvph tceav twph
CYUSB3035 document number: 001-84160 rev. *b page 29 of 50 note 6. all parameters guaranteed by design and validated through characterization. table 11. asynchronous admux timing parameters [6] parameter description min max units notes admux asynchronous read access timing parameters trc read cycle time (address valid to address valid) 54.5 ? ns this parameter is dependent on when the p-port processors deasserts oe# tacc address valid to data valid ? 32 ns tco ce# assert to data valid ? 34.5 ns tavoe adv# deassert to oe# assert 2 ? ns tolz oe# assert to data low-z 0 ? ns toe oe# assert to data valid ? 25 ns thz read cycle end to data high-z ? 22.5 ns admux asynchronous write access timing parameters twc write cycle time (add ress valid to address valid) ? 52.5 ns taw address valid to write end 30 ? ns tcw ce# assert to write end 30 ? ns tavwe adv# deassert to we# assert 2 ? ns twp we# low pulse width 20 ? ns twph we# high pulse width 10 ? ns tds data valid setup to we# deassert 18 ? ns tdh data valid hold from we# deassert 2 ? ns admux asynchronous common read/write access timing parameters tavs address valid setup to adv# deassert 5 ? ns tavh address valid hold from adv# deassert 2 ? ns tvp adv# low pulse width 7.5 ? ns tcph ce# high pulse width 10 ? ns tvph adv# high pulse width 15 ? ns tceav ce# assert to adv# assert 0 ? ns
CYUSB3035 document number: 001-84160 rev. *b page 30 of 50 synchronous admux timing figure 20. synchronous admux interface ? read cycle timing figure 21. synchronous admux interface ? write cycle timing a[0:7]/dq[0:15] adv# ce# oe# rdy tavoe ts valid address ts th ts th tco tohz tclkh tclkl clk tch tkw tkw tolz tclk 2- cycle latency from oe# to data we# (high) valid data note: 1) external p-port processor and fx3s operate on the same clock edge 2) external processor sees rdy assert 2 cycles after oe # asserts andand sees rdy deassert a cycle after the data appears on th e output 3) valid output data appears 2 cycle after oe # asserted. the data is held until oe # deasserts 4) two cycle latency is shown for 0-100 mhz operation. latency can be reduced by 1 cycle for operations at less than 50 mhz (t his 1 cycle latency is not supported by the bootloader) a[0:7]/dq[0:15] adv# ce# we# rdy tavwe ts valid address ts valid data th ts th tdh tds tclk clk tkw note: 1) external p-port processor and fx3s operate on the same clock edge 2) external processor sees rdy assert 2 cycles after we # asserts and deassert 3 cycles after the edge sampling the data. 3) two cycle latency is shown for 0-100 mhz operation. latency can be reduced by 1 cycle for operations at less than 50 mhz (th is 1 cycle latency is not supported by the bootloader) ts th tkw 2-cycle latency between we# and data being latched 2-cycle latency between this clk edge and rdy deassertion seen by the host
CYUSB3035 document number: 001-84160 rev. *b page 31 of 50 figure 22. synchronous admux interface ? burst read timing figure 23. sync admux interface ? burst write timing a[0:7]/dq[0:15] adv# ce# oe# rdy tavoe ts valid address ts d0 d1 th ts th tch tco d2 tclkh tclkl tclk clk d3 2-cycle latency from oe# to data tkw tkw thz tolz note: 1) external p-port processor and fx3s work operate on the same clock edge 2) external processor sees rdy assert 2 cycles after oe # asserts andand sees rdy deassert a cycle after the last burst data ap pears on the output 3) valid output data appears 2 cycle after oe # asserted. the last burst data is held until oe # deasserts 4) burst size of 4 is shown. transfer size for the operation must be a multiple of burst size. burst size is usually power of 2. rdy will not deassert in the middle of the burst. 5) external processor cannot deassert oe in the middle of a burst. if it does so, any bytes remaining in the burst packet could get lost. 6) two cycle latency is shown for 0-100 mhz operation. latency can be reduced by 1 cycle for operations at less than 50 mhz (this 1 cycle latency is not supported by the b ootloader) a[0:7]/dq[0:15] adv# ce# we# tavwe ts valid address ts d1 th ts th tdh tds d3 tdh tclkh tclkl tclk clk d0 rdy tkw d2 2-cycle latency between we# and data being latched tkw 2-cycle latency between this clk edge and rdy deassertion seen by the host note: 1) external p-port processor and fx3s operate on the same clock edge 2) external processor sees rdy assert 2 cycles after we # asserts and deasserts 3 cycles after the edge sampling the last burst data. 3) transfer size for the operation must be a multiple of burst size. burst size is usually power of 2. rdy will not deassert i n the middle of the burst. burst size of 4 is shown 4) external processor cannot deassert we in the middle of a burst. if it does so, any bytes remaining in the burst packet could get lost. 5)two cycle latency is shown for 0-100 mhz operation. latency c an be reduced by 1 cycle for operations at less than 50 mhz (thi s 1 cycle latency is not supported by the bootloader)
CYUSB3035 document number: 001-84160 rev. *b page 32 of 50 table 12. synchronous admux timing parameters [3] parameter description min max unit freq interface clock frequency ? 100 mhz tclk clock period 10 ? ns tclkh clock high time 4 ? ns tclkl clock low time 4 ? ns ts ce#/we#/dq setup time 2 ? ns th ce#/we#/dq hold time 0.5 ? ns tch clock to data output hold time 0 ? ns tds data input setup time 2 ? ns tdh clock to data input hold 0.5 ? ns tavdoe adv# high to oe# low 0 ? ns tavdwe adv# high to we# low 0 ? ns thz ce# high to data high-z ? 8 ns tohz oe# high to data high-z ? 8 ns tolz oe# low to data low-z 0 ? ns tkw clock to rdy valid ? 8 ns note 7. all parameters guaranteed by design and validated through characterization.
CYUSB3035 document number: 001-84160 rev. *b page 33 of 50 slave fifo interface synchronous slave fifo sequence description fifo address is stable and slcs is asserted sloe is asserted. sloe is an output-enable only, whose sole function is to drive the data bus. slrd is asserted the fifo pointer is updated on the rising edge of the pclk, while the slrd is asserted. this starts the propagation of data from the newly addressed location to the data bus. after a propagation delay of tco (meas ured from the rising edge of pclk), the new data value is present. n is the first data value read from the fifo. to have data on the fifo data bus, sloe must also be asserted. the same sequence of events is shown for a burst read. note for burst mode, the slrd# and sloe# are asserted during the entire duration of the read. when sloe# is asserted, the data bus is driven (with dat a from the previously addressed fifo). for each subsequent rising edge of pclk, while the slrd# is asserted, the fifo poin ter is incremented and the next data value is placed on the data bus. figure 24. synchronous slave fifo read mode synchronous read cycle timing pclk fifo addr t cyc t ch t cl t as slcs slrd t rds t rdh sloe flaga (dedicated thread flag for an) ( 1 = not empty 0= empty) t oelz data out high-z data driven:d n (an) t cdh t oez t oez 3- cycle latency from addr to data t co t oelz an am d n+1 (an) d n (am) d n+1 (am) d n+2 (am) slwr (high) t ah flagb (dedicated thread flag for am) ( 1 = not empty 0= empty) 2-cycle latency from slrd to data t cflg t cflg 2 cycle latency from slrd to flag
CYUSB3035 document number: 001-84160 rev. *b page 34 of 50 synchronous slave fifo write sequence description fifo address is stable and the signal slcs# is asserted external master or peripheral out puts the data to the data bus slwr# is asserted while the slwr# is asserted, data is written to the fifo and on the rising edge of the pclk, the fifo pointer is incremented the fifo flag is updated after a delay of t wflg from the rising edge of the clock the same sequence of events is also shown for burst write note for the burst mode, slwr# and slcs# are asserted for the entire duration, during which all the required data values are written. in this burst write mode, after the slwr# is asserted, the data on the fifo data bus is written to the fifo on every rising edge of pclk. the fifo pointer is updated on each rising edge of pclk. short packet : a short packet can be co mmitted to the usb host by using the pktend#. the external device or processor should be designed to assert the pktend# along with the last word of data and slwr# pulse corresponding to the last word. the fifoaddr lines must be held constant during the pktend# assertion. zero-length packet : the external device or processor can signal a zero-length packet (zlp) to fx3s simply by asserting pktend#, without asserting slwr#. slcs# and address must be driven as shown in figure 25 on page 34. flag usage : the flag signals are monitored for flow control by the external processor. flag signals are outputs from fx3s that may be configured to show empt y, full, or partial status for a dedicated thread or the current thread that is addressed. figure 25. synchronous slave fifo write mode synchronous write cycle timing pclk fifo addr t cyc t ch t cl t as slcs slwr data in high-z d n (an) t dh t ds t dh t ds t dh t wrs t wrh t peh pktend d n (am) d n+1 (am) d n+2 (am) sloe (high) an am t ah t pes flaga dedicated thread flag for an (1 = not full 0= full) t cflg flagb current thread flag for am (1 = not full 0= full) t cflg 3 cycle latency from slwr # to flag 3 cycle latency from slwr # to flag pclk fifo addr t cyc t ch t cl t as slcs slwr (high) data in high-z pktend sloe (high) an t ah flaga dedicated thread flag for an (1 = not full 0= full) flagb current thread flag for am (1 = not full 0= full) t peh t pes synchronous zlp write cycle timing t cflg
CYUSB3035 document number: 001-84160 rev. *b page 35 of 50 . asynchronous slave fifo read sequence description fifo address is stable and the slcs# signal is asserted. sloe# is asserted. this resu lts in driving the data bus. slrd # is asserted. data from the fifo is driven af ter assertion of slrd#. this data is valid after a propagation delay of trdo from the falling edge of slrd#. fifo pointer is incremen ted on deassertion of slrd# in figure 26 on page 36, data n is the first valid data read from the fifo. for data to appear on the data bus during the read cycle, sloe# must be in an asserted state. slrd# and sloe# can also be tied. the same sequence of events is also shown for a burst read. note in the burst read mode, dur ing sloe# assertion, the data bus is in a driven state (data is driven from a previously addressed fifo). after assertion of slrd# data from the fifo is driven on the data bus (sloe# must also be asserted). the fifo pointer is incremented after deassertion of slrd#. note 8. all parameters guaranteed by design and validated through characterization. table 13. synchronous slave fifo parameters [8] parameter description min max units freq interface clock frequency ? 100 mhz tcyc clock period 10 ? ns tch clock high time 4 ? ns tcl clock low time 4 ? ns trds slrd# to clk setup time 2 ? ns trdh slrd# to clk hold time 0.5 ? ns twrs slwr# to clk setup time 2 ? ns twrh slwr# to clk hold time 0.5 ? ns tco clock to valid data ? 8 ns tds data input setup time 2 ? ns tdh clk to data input hold 0.5 ? ns tas address to clk setup time 2 ? ns tah clk to address hold time 0.5 ? ns toelz sloe# to data low-z 0 ? ns tcflg clk to flag output propagation delay ? 8 ns toez sloe# deassert to data hi z ? 8 ns tpes pktend# to clk setup 2 ? ns tpeh clk to pktend# hold 0.5 ? tcdh clk to data output hold 2 ? ns note three-cycle latency from addr to data/flags
CYUSB3035 document number: 001-84160 rev. *b page 36 of 50 figure 26. asynchronous slave fifo read mode asynchronous slave fifo write sequence description fifo address is driven and slcs# is asserted slwr# is asserted. slcs# must be asserted with slwr# or before slwr# is asserted data must be present on the tw rs bus before the deasserting edge of slwr# deassertion of slwr# causes the data to be written from the data bus to the fifo, and then th e fifo pointer is incremented the fifo flag is updated after the twflg from the deasserting edge of slwr. the same sequence of events is shown for a burst write. note that in the burst write mo de, after slwr# deassertion, the data is written to the fifo, and then the fifo pointer is incre- mented. short packet : a short packet can be co mmitted to the usb host by using the pktend#. the external device or processor should be designed to assert the pktend# along with the last word of data and slwr# pulse corresponding to the last word. the fifoaddr lines must be held constant during the pktend# assertion. zero-length packet : the external device or processor can signal a zero-length packet (zlp) to fx3s simply by asserting pktend#, without asserting slwr#. slcs# and the address must be driven as shown in figure 27 on page 37. flag usage : the flag signals are monitored by the external processor for flow control. flag signals are fx3s outputs that can be configured to show empty, full, and partial status for a dedicated address or the current address. fifo addr t as slcs slrd t rdl sloe flaga dedicated thread flag for an (1=not empty 0 = empty) t oe data out high-z t ah d n (an) t rdo t oe t rdo t oh t oh t rdh t rdo t lz d n (an) d n (am) d n+1 (am) d n+2 (am) slwr (high) an am flagb dedicated thread flag for am (1=not empty 0 = empty) t rflg t flg
CYUSB3035 document number: 001-84160 rev. *b page 37 of 50 figure 27. asynchronous slave fifo write mode asynchronous write cycle timing fifo addr t as slcs slwr t wrl data in high-z t ah d n (an) t wr s t wr s t wrh t wrh t wrh pktend d n (am) d n+1 (am) d n+2 (am) sloe (high) an am flaga dedicated thread flag for an (1=not full 0 = full) t wflg t wflg flagb dedicated thread flag for am (1=not full 0 = full) t flg t wrpe twrpe: slwr# de-assert to pktend deassert = 2ns min (this means that pktend should not be be deasserted before slwr#) note: pktend must be asserted at the same time as slwr#. asynchronous zlp write cycle timing fifo addr t as slcs slwr (high) data in high-z t ah sloe (high) an flaga dedicated thread flag for an (1=not full 0 = full) flagb dedicated thread flag for am (1=not full 0 = full) pktend t pel t peh t wflg t peh
CYUSB3035 document number: 001-84160 rev. *b page 38 of 50 storage port timing the s0-port and s1-port support the mmc specificatio n version 4.41 and sd specification version 3.0. ta b l e 1 5 lists the timing parameters for s-port of the fx3s device. note 9. all parameters guaranteed by design and validated through characterization. table 14. asynchronous slave fifo parameters [9] parameter description min max units trdi slrd# low 20 ? ns trdh slrd# high 10 ? ns tas address to slrd#/slwr# setup time 7 ? ns tah slrd#/slwr#/pktend to address hold time 2 ? ns trflg slrd# to flags output propagation delay ? 35 ns tflg addr to flags output propagation delay ? 22.5 trdo slrd# to data valid ? 25 ns toe oe# low to data valid ? 25 ns tlz oe# low to data low-z 0 ? ns toh sloe# deassert data output hold ? 22.5 ns twri slwr# low 20 ? ns twrh slwr# high 10 ? ns twrs data to slwr# setup time 7 ? ns twrh slwr# to data hold time 2 ? ns twflg slwr#/pktend to flags output propagation delay ? 35 ns tpei pktend low 20 ? ns tpeh pktend high 7.5 ? ns twrpe slwr# deassert to pktend deassert 2 ? table 15. s-port timing parameters [10] parameter description min max units mmc-20 tsdis cmd host input setup time for cmd 4.8 ? ns tsdis dat host input setup time for dat 4.8 ? ns tsdih cmd host input hold time for cmd 4.4 ? ns tsdih dat host input hold time for dat 4.4 ? ns tsdos cmd host output setup time for cmd 5 ? ns tsdos dat host output setup time for dat 5 ? ns tsdoh cmd host output hold time for cmd 5 ? ns tsdoh dat host output hold time for dat 5 ? ns tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 50 ? ns sdfreq clock frequency ? 20 mhz tsdclkod clock duty cycle 40 60 % mmc-26 tsdis cmd host input setup time for cmd 10 ? ns tsdis dat host input setup time for dat 10 ? ns
CYUSB3035 document number: 001-84160 rev. *b page 39 of 50 tsdih cmd host input hold time for cmd 9 ? ns tsdih dat host input hold time for dat 9 ? ns tsdos cmd host output setup time for cmd 3 ? ns tsdos dat host output setup time for dat 3 ? ns tsdoh cmd host output hold time for cmd 3 ? ns tsdoh dat host output hold time for dat 3 ? ns tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 38.5 ? ns sdfreq clock frequency ? 26 mhz tsdclkod clock duty cycle 40 60 % mc-hs tsdis cmd host input setup time for cmd 4 ? ns tsdis dat host input setup time for dat 4 ? ns tsdih cmd host input hold time for cmd 3 ? ns tsdih dat host input hold time for dat 3 ? ns tsdos cmd host output setup time for cmd 3 ? ns tsdos dat host output setup time for dat 3 ? ns tsdoh cmd host output hold time for cmd 3 ? ns tsdoh dat host output hold time for dat 3 ? ns tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 19.2 ? ns sdfreq clock frequency ? 52 mhz tsdclkod clock duty cycle 40 60 % mmc-ddr52 tsdis cmd host input setup time for cmd 4 ? ns tsdis dat host input setup time for dat 0.56 ? ns tsdih cmd host input hold time for cmd 3 ? ns tsdih dat host input hold time for dat 2.58 ? ns tsdos cmd host output setup time for cmd 3 ? ns tsdos dat host output setup time for dat 2.5 ? ns tsdoh cmd host output hold time for cmd 3 ? ns tsdoh dat host output hold time for dat 2.5 ? ns tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 19.2 ? ns sdfreq clock frequency ? 52 mhz tsdclkod clock duty cycle 45 55 % sd-default speed (sdr12) tsdis cmd host input setup time for cmd 24 ? ns tsdis dat host input setup time for dat 24 ? ns table 15. s-port timing parameters [10] (continued) parameter description min max units
CYUSB3035 document number: 001-84160 rev. *b page 40 of 50 tsdih cmd host input hold time for cmd 2.5 ? ns tsdih dat host input hold time for dat 2.5 ? ns tsdos cmd host output setup time for cmd 5 ? ns tsdos dat host output setup time for dat 5 ? ns tsdoh cmd host output hold time for cmd 5 ? ns tsdoh dat host output hold time for dat 5 ? ns tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 40 ? ns sdfreq clock frequency ? 25 mhz tsdclkod clock duty cycle 40 60 % sd-high-speed (sdr25) tsdis cmd host input setup time for cmd 4 ? ns tsdis dat host input setup time for dat 4 ? ns tsdih cmd host input hold time for cmd 2.5 ? ns tsdih dat host input hold time for dat 2.5 ? ns tsdos cmd host output setup time for cmd 6 ? ns tsdos dat host output setup time for dat 6 ? ns tsdoh cmd host output hold time for cmd 2 ? ns tsdoh dat host output hold time for dat 2 ? ns tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 20 ? ns sdfreq clock frequency ? 50 mhz tsdclkod clock duty cycle 40 60 % sd-sdr50 tsdis cmd host input setup time for cmd 1.5 ? ns tsdis dat host input setup time for dat 1.5 ? ns tsdih cmd host input hold time for cmd 2.5 ? ns tsdih dat host input hold time for dat 2.5 ? ns tsdos cmd host output setup time for cmd 3 ? ns tsdos dat host output setup time for dat 3 ? ns tsdoh cmd host output hold time for cmd 0.8 ? ns tsdoh dat host output hold time for dat 0.8 ? ns tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 10 ? ns sdfreq clock frequency 100 mhz tsdclkod clock duty cycle 40 60 % sd-ddr50 tsdis cmd host input setup time for cmd 4 ? ns tsdis dat host input setup time for dat 0.92 ? ns table 15. s-port timing parameters [10] (continued) parameter description min max units
CYUSB3035 document number: 001-84160 rev. *b page 41 of 50 serial peripherals timing i 2 c timing figure 28. i 2 c timing definition tsdih cmd host input hold time for cmd 2.5 ? ns tsdih dat host input hold time for dat 2.5 ? ns tsdos cmd host output setup time for cmd 6 ? ns tsdos dat host output setup time for dat 3 ? ns tsdoh cmd host output hold time for cmd 0.8 ? ns tsdoh dat host output hold time for dat 0.8 ? ns tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 20 ? ns sdfreq clock frequency ? 50 mhz tsdclkod clock duty cycle 45 55 % table 15. s-port timing parameters [10] (continued) parameter description min max units note 10. all parameters guaranteed by design and validated through characterization.
CYUSB3035 document number: 001-84160 rev. *b page 42 of 50 note 11. all parameters guaranteed by design and validated through characterization. table 16. i 2 c timing parameters [11] parameter description min max units i 2 c standard mode parameters fscl scl clock frequency 0 100 khz thd:sta hold time start condition 4 ? s tlow low period of the scl 4.7 ? s thigh high period of the scl 4 ? s tsu:sta setup time for a repeated start condition 4.7 ? s thd:dat data hold time 0 ? s tsu:dat data setup time 250 ? ns tr rise time of both sda and scl signals ? 1000 ns tf fall time of both sda and scl signals ? 300 ns tsu:sto setup time for stop condition 4 ? s tbuf bus free time between a stop and start condition 4.7 ? s tvd:dat data valid time ? 3.45 s tvd:ack data valid ack ? 3.45 s tsp pulse width of spikes that must be suppressed by input filter n/a n/a i 2 c fast mode parameters fscl scl clock frequency 0 400 khz thd:sta hold time start condition 0.6 ? s tlow low period of the scl 1.3 ? s thigh high period of the scl 0.6 ? s tsu:sta setup time for a repeated start condition 0.6 ? s thd:dat data hold time 0 ? s tsu:dat data setup time 100 ? ns tr rise time of both sda and scl signals ? 300 ns tf fall time of both sda and scl signals ? 300 ns tsu:sto setup time for stop condition 0.6 ? s tbuf bus free time between a stop and start condition 1.3 ? s tvd:dat data valid time ? 0.9 s tvd:ack data valid ack ? 0.9 s tsp pulse width of spikes that must be suppressed by input filter 0 50 ns i 2 c fast mode plus parameters (not supported at i2c_vddq=1.2 v) fscl scl clock frequency 0 1000 khz thd:sta hold time start condition 0.26 ? s tlow low period of the scl 0.5 ? s thigh high period of the scl 0.26 ? s tsu:sta setup time for a repeated start condition 0.26 ? s thd:dat data hold time 0 ? s tsu:dat data setup time 50 ? ns
CYUSB3035 document number: 001-84160 rev. *b page 43 of 50 i 2 s timing diagram figure 29. i 2 s transmit cycle tr rise time of both sda and scl signals ? 120 ns tf fall time of both sda and scl signals ? 120 ns tsu:sto setup time for stop condition 0.26 ? s tbuf bus-free time between a stop and start condition 0.5 ? s tvd:dat data valid time ? 0.45 s tvd:ack data valid ack ? 0.55 s tsp pulse width of spikes that must be suppressed by input filter 0 50 ns table 16. i 2 c timing parameters [11] (continued) parameter description min max units t t t tr t tf t tl t thd t td t th sck sa, ws (output) note 12. all parameters guaranteed by design and validated through characterization. table 17. i 2 s timing parameters [12] parameter description min max units tt i 2 s transmitter clock cycle ttr ? ns ttl i 2 s transmitter cycle low period 0.35 ttr ? ns tth i 2 s transmitter cycle high period 0.35 ttr ? ns ttr i 2 s transmitter rise time ? 0.15 ttr ns ttf i 2 s transmitter fall time ? 0.15 ttr ns tthd i 2 s transmitter data hold time 0 ? ns ttd i 2 s transmitter delay time ? 0.8tt ns note tt is selectable through clock gears. max ttr is designed for 96-khz codec at 32 bits to be 326 ns (3.072 mhz).
CYUSB3035 document number: 001-84160 rev. *b page 44 of 50 spi timing specification figure 30. spi timing lsb lsb msb msb lsb lsb msb msb t lead t sck t sdd t hoi t wsck t wsck t lag t d v t rf t ssnh t dis t sdi t lead t sck t wsck t wsck t lag t rf t ssnh t sdi t dis t dv t hoi ssn (output) sck (cpol=0, output) sck (cpol=1, output) miso (input) mosi (output) ssn (output) sck (cpol=0, output) sck (cpol=1, output) miso (input) mosi (output) spi master timing for cpha = 0 spi master timing for cpha = 1 t di t di
CYUSB3035 document number: 001-84160 rev. *b page 45 of 50 reset sequence fx3s?s hard reset sequence requirements are specified in this section. notes 13. all parameters guaranteed by design and validated through characterization. 14. depends on lag and lead sett ing in the spi_config register. table 18. spi timing parameters [13] parameter description min max units fop operating frequency 0 33 mhz tsck cycle time 30 ? ns twsck clock high/low time 13.5 ? ns tlead ssn-sck lead time 1/2 tsck [14 ] -5 1.5 tsck [14] + 5 ns tlag enable lag time 0.5 1.5 tsck [14] +5 ns trf rise/fall time ? 8 ns tsdd output ssn to valid data delay time ? 5 ns tdv output data valid time ? 5 ns tdi output data invalid 0 ? ns tssnh minimum ssn high time 10 ? ns tsdi data setup time input 8 ? ns thoi data hold time input 0 ? ns tdis disable data output on ssn high 0 ? ns table 19. reset and standby timing parameters parameter definition conditions min (ms) max (ms) trpw minimum reset# pulse width clock input 1 ? crystal input 1 ? trh minimum high on reset# ? 5 ? trr reset recovery time (after which boot loader begins firmware download) clock input 1 ? crystal input 5 tsby time to enter standby/suspend (from the time main_clock_en/ main_power_en bit is set) ??1 twu time to wakeup from standby clock input 1 ? crystal input 5 ? twh minimum time before standby/suspend source may be reasserted ?5?
CYUSB3035 document number: 001-84160 rev. *b page 46 of 50 figure 31. reset sequence vdd (core) xvddq xtalin/ clkin reset # mandatory reset pulse hard reset trpw trh standby/ suspend source standby/suspend source is asserted (main_power_en/ main_clk_en bit is set) standby/suspend source is deasserted tsby twu xtalin/ clkin must be stable before exiting standby/suspend trr twh
CYUSB3035 document number: 001-84160 rev. *b page 47 of 50 package diagram figure 32. 121-ball fbga (10 10 1.2 mm (0.30 mm ball diameter)) package outline, 001-54471 001-54471 *d
CYUSB3035 document number: 001-84160 rev. *b page 48 of 50 ordering information ordering code definitions table 20. device ordering information ordering code sram (kb) storage ports hs-usb otg gpif ii data bus width package type CYUSB3035-bzxi 512 2 yes 16-bit 121-ball bga CYUSB3035-bzxc 512 2 yes 16-bit 121-ball bga cyusb3033-bzxc 512 1 yes 16-bit 121-ball bga cyusb3031-bzxc 256 1 no 16-bit 121-ball bga cy marketing code: usb = usb controller usb company id: cy = cypress package type: bga 3 i/c temperature range : industrial/commercial base part number for usb 3.0 xxx bzx marketing part number
CYUSB3035 document number: 001-84160 rev. *b page 49 of 50 acronyms document conventions units of measure acronym description dma direct memory access hnp host negotiation protocol mmc multimedia card mtp media transfer protocol pll phase locked loop pmic power management ic sd secure digital sd secure digital sdio secure digital input / output slc single-level cell slcs slave chip select sloe slave output enable slrd slave read slwr slave write spi serial peripheral interface srp session request protocol usb universal serial bus wlcsp wafer level chip scale package symbol unit of measure c degree celsius a microamperes s microseconds ma milliamperes mbps megabits per second mbps megabytes per second mhz mega hertz ms milliseconds ns nanoseconds ohms pf pico farad vvolts
document number: 001-84160 rev. *b revised june 20, 2013 page 50 of 50 ez-usb? is a trademark and west bridge ? is a registered trademark of cypress semiconductor corp. all products and company names mentioned in this document may be the t rademarks of their respective holders. CYUSB3035 ? cypress semiconductor corporation, 2012-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support document title: CYUSB3035, ez-usb ? fx3s superspeed usb controller document number: 001-84160 revision ecn orig. of change submission date description of change ** 3786345 samt 12/06/2012 new data sheet. *a 3900859 samt 02/11/2013 updated ordering information (updated part numbers). *b 4027072 samt 06/20/2013 added new mpns in ordering information .

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